Peak detection circuits

ABSTRACT

A peak detection circuit has two capacitive storage stages. The first storage stage has a fixed discharge time constant, and the second storage stage has two switchably selectable discharge time constants, one of which is less than that of the first storage stage and the other greater. During measurement of a peak level the greater time constant is used to provide an accurate measurement, but between successive measurements the lesser time constant is selected to reduce the waiting time normally required between such measurements.

'[72] Inventor: George A A United- States Patent Lloyd [54] PEAK DETECTION CIRCUITS Howard Lloyd, Hert- [211 App]. No.: 121,769

[30] Foreign Application Priority Data March 7, 1.970 Great Britain...,...'...1 1,031/70 [52] US. Cl ..307/2 35-A, 307/246, 328/146,

' 1 328/151 [51] Int. Cl. ..H03k 17/28, H03k 17/30 7, [58] Field of Search ..30.7/235, 238, 246; 328/146,

1s] 3,699,357 1451 Oct. 17,1972

Bjorkman et al., Peak Picking and Noise'suppression Circuitry IBM Technical Disclosure Bulletin,

' Vol.9, No; 6; p 588- 589,11/1966 Kennedy, Variable Threshold Control, lBM- Technical Disclosure Bulletin, Vol. 8, No. 4, p. 692- 693, 9/1965. a

Primary Examiner-Herman Karl Saalbach Assistant Examiner--L. N. Anagnos Attorney-Baldwin, Wight & Brown [5 7] 1 ABSTRACT A peak detection circuit has twocapacitive storage stages. The first storage stage has a fixed discharge time constant, and-the second storage stage has two [56] r RefelTences l switchably selectable discharge time constants, one of UNITED STATES PATENTS ,which is less than that'of the first storage stage and the other greater. During measurement of a peak level the 1 v 1 1 13 1968 Bedingfield 328/151 X greater time constant is used to provide an accurate 3,470,432 9/1969 'Koll'lowski 307/246 x measurement, but between successive measurements Lukoff .J the lesser constant is selected to reduce wait- I Wallace, Jr. normally required between such measure- 3,145,345 8/1964 Squillaro et al........328/l51 X menm 3,287,570 11/1966 Wilson ..307/235 k 3,328,705 6/1967 Eubanks ..328/151 8 Claims, 1 Drawing Figure 1.1? a: W (f TI 62 0 a3 This invention relates to peak detection circuits, particularly to A.C. peak voltmeters in which a potential indicative of a peak voltage to be measured is capacitively stored betweensuccessive voltage peaks.

For peak detection circuits of this kind to operate satisfactorily it is a'basic requirement of the circuit that the stored potential indicative of a peak voltage to be measured does not appreciably decay between successive voltage peaks. This requirement can impose stringent design requirements on peak detection circuits which provide satisfactory operation at very low input signal frequencies (say below Hz) and/or at low input levels. To ensure that the capacitively stored charge does not appreciably decay between successive Preferably the said transistor is controlled by the output of a two input comparator, one input of which is fed with a potential representative of that stored by the-first storage stage, and the other input of which is fed with a reference potential.

Preferably again the said peak detection circuit inv capacitive storage stage to the firstcapacitive storage stage whereby the charging circuit for the said first stage becomes non-charging when the said signal level voltage peaks it is necessary to provide that any discharge path for the storage capacitor has a very high impedance and to arrange that in operation the capacitor is only lightly loaded by any succeeding stage of the peak detection circuit.

Whilst circuits of this kind can be designed which operate well atlow frequencies, such circuits generally have the disadvantage that when an input signal (for example a voltage to be measured) is removed or reduced the charge storing capacitor takes an excessively long time to discharge. The discharge time can be many seconds and during this time it is inadvisable to use the peak detector circuit for measuring other signals since an erroneous peak voltage indication could, under these circumstances, be obtained. .In general, the better the'performance of the peak detector circuit, the longer does the charge storing capacitor take to discharge and the greater is the aforementioned disadvantage.

An object ofthis invention is toprovide a peak detectioncircuitwhich minimizes the aforementioned disadvantage without degrading the performance of the circuit.

J According to this invention a peak detection circuit of the kind having a capacitive storage arrangementfor storing a potential representative of the peak input signal level includes a first capacitive storage stage for storing a representative potential, and a second capacitive storage stage connected to the first stage, and also for storing a representative potential, the second stage having a discharge time constant which is long relative to that of the first stage and means for reducing this discharge time constant when the potential stored by the first stage has decayed below a selected level which is lower than that stored by the second stage.

2 Preferably the discharge time constantto which the second capacitive storage stage is reduced, when the potential stored by the first stage has decayed below a selected level which is lower than that stored by the second stage, is short relative to the discharge time constant of the first stage.

Preferably the means for reducing the discharge time constant of the second capacitive storage stage when the. potential stored by the first stage has decayed below a selected level which is lower than that stored bythe second stage, includes a transistor which in dependence on the potential stored by the first stage, provides a relatively low impedance discharge path for the second stage.

tor being connected to means for controlling the charging current of the first capacitive storage stage such that if a the input signal is greater than the signal level on the feedback loop the means allowsthe charging current to flow, whereas if the input signal is lower than the feedback signal the means cuts off the charging current.

Preferably the said means for controlling the chargnected to one side of a first storage capacitor C1, the

other side of which is connected to'earth potential. The

collector of transistor T1 is also connected to the input ofa second amplifier G2, the output of which is con nected to one side of a secondstorage capacitor C2 via a diode D. The other side of capacitor C2 is also connected to earth potential. The junction between the diode D andthe capacitor C2 is connected to the input of a third amplifier G3, the output of which provides the output signal of the whole peak detector circuit,

and which is used in addition to provide a feedback signal to the remaining input of the differential amplifier G1. Connected in shunt with amplifier G2 and the diode D is a fourth amplifier G4 and a n.p.n. transistor T2. The amplifier G4 is a differential amplifier one input of which is connected to the collector oftransistor T1 and also via a resistor R to a source of potential Vvolts and the other input of which is connected to a source of reference potential V volts. The resistor R in combination with the capacitor C1 provides the first capacitive storage stage. The output of amplifier G4 is connected to the base of the transistor T2, the emitter of which is at earth potential and the collector of which is connected to the input of amplifier G3. The four amplifiers G1, G2, G3 and G4 all have a very high input impedance and the discharge path of capacitorCl is therefore provided mainly by resistor R the valve of which effectively determines the discharge time constant associated with a given value In operationcapacitor C1 is assumed to be initially.

discharged, and consequently the input signal to the associated one of the inputs of amplifier G4 is substantially at earth potential. The polarity of the reference voltage'V is chosen so that under these conditions transistor T2 is maintained in a conductive state. This is necessary to ensure that capacitor C2 is also initially discharged.

when an input signal (being an A. C. voltage whose peak value is to be measured) is applied to amplifier G1, the signal is amplified'and applied to the base of transistor T1 and causes capacitor C1 to charge up from the positive supply potential V volts via this transistor. The discharge time constant of this capacitor C1 is determined by the value of the capacitor C1 and the resistor R, and is arranged to provide sufficient smoothing to ensure that the resulting output signal of amplifier G4 is of sufficient magnitude to switch transistor T2 and maintain this transistor in a non-conductive state. The partly smoothed signal is applied to the input of amplifier G2, the output of which charges capacitor C2 via the diode D. Since transistor T2 is held in a non-conductive state there is, assuming that the input impedance of amplifier G3 is very high, no low impedance discharge path for capacitor C2, and it therefore has associated with it a very long time constant. Thus the capacitor C2 provides a very high degree of smoothing and maintains a peak voltage with a minimum of ripple. This voltage is amplified by amplifier G3 and is utilized via output terminal O.P. as required, for example by a suitable meter for display or otherwise for readout purposes. The amplifying system is provided with a feedback loop from the output of amplifier G3 to an input of amplifier G1.

When the input signal is removed or reduced the charge retained by capacitor C2 provides a feedback signal via amplifier G3 to amplifier G1 which switches transistor T1 off, and allows capacitor C1 to discharge through resistor R. This in turn provides a signal via amplifier G4 which switches transistor T2 into a conductive state and therefore transistor T2 provides the means for reducing the discharge time constant of the second capacitive storage stage. Capacitor C2 is thereby rapidly discharged, and the output signal at terminal 0.1. is reduced equally rapidly. Thus, the minimum time interval between successive measurements of peak voltage without risk of error is determined by the discharge time constant of the capacitor C1 resistor R combination. As stated previously this time constant may be made as short as is desired provided that the degree of smoothing thereby obtained is sufficient to prevent the differential amplifier G4 and hence transistor T2 inadvertently being switched by the negative going portions of the input signal.

Iclaim: l. A peak detection circuit, of the kind having a capacitive storage arrangement for storing a potential representative of the peak level of an input signal, including a first capacitive storage stage for storing a first potential representative of the peak level of the input signal and having'a selected discharge time constant, a second capacitive storage stage, connected to the first stage, for storing a second potential representative of the peak input signal level, the second stage having a discharge time constant which is large relative to that of the first stage, means for comparing the first potential with a reference potential which is lower than the second potential, and means for reducing the discharge time constant of the second stage in response to decay of the first potential below the reference potential.

2. A peak detection circuit as claimed in claim 1 wherein the discharge time constant to which the second capacitive storage stage is reduced, when the potential stored by the first stage is reduced, when the potential stored by the first stage has decayed below said reference potential, vis short relative to the discharge time constant of the first stage.

3.'A peak detection circuit as claimed in claim 2 wherein the means for reducing the discharge time constant of the second capacitive storage stage when the potential stored by the first stage has decayed below said reference potential, includes a transistor which in dependence on the potential stored by the first stage, provides a relatively low impedance discharge path for the second stage.

4. A peak detection circuit as claimed in claim 2 including a feedback loop for feeding a signal level representative of the potential stored by the second capacitive storage stage to the first capacitive storage stage whereby the charging circuit for the said first stage becomes non-charging when the said signal level representative of the potential stored by the second stage exceeds the input signal level.

5. A peak detection circuit 'as claimed in claim 4 including a two-input comparator the said feedback loop and the input for said input signal each being connected to a respective input of the comparator and the comparator being connected to means for controlling the charging current of the first capacitive storage stage such that if the input signal is greater than the signal level on the feedback loop the means for controlling allows charging current to flow whereas if the input signal is lower than the feedback signal the means for controlling cuts off the charging current.

6. A peak detection circuit as claimed in claim 5 in which the said means for controlling the charging current comprises a transistor switch.

7. A peak detector circuit as claimed in claim 3 in which the said transistor is controlled by the output of a two input comparator, one input of which is fed with a potential representative of that stored by the first storage stage, and-the other input of which is fed with a reference potential.

8. A peak detection circuit comprising, in combination;

a first capacitive storage device;

means for providing a fixed impedance discharge path to fixed potential for said first capacitive storage device and having, in combination therewith, a fixed discharge time constant;

means for receiving a periodic input signal and for charging said first capacitive storage device in 3,699,357 6 response to and to a peak voltage level related to on said first capacitive storage device and for conthe peak level of such input signal; trolling said variable impedance means to. provide a Second Capacitive Storage device; a first discharge time constant for said second high impedance amplifier means having an input capacitive storage device which is long compared connectefi to sfaid first cavacifiye storage device 5 to said fixed discharge time constant when the infor charging sald second capacmve storage dev'ce stantaneous voltage level on said first capacitive to a i related 5 peak voltage. levg storage device is above a selected value and to proto which said first capacitive storage device is charged vide a second discharge time constant which is variable impedance means for providing a discharge 10 Short F fixed discharge path to fixed potential for said Second capacitive stant when said instantaneous voltage level decays storage device. and below said selected value. means for comparing the instantaneous voltage level 

1. A peak detection circuit, of the kind having a capacitive storage arrangement for storing a potential representative of the peak level of an input signal, including a first capacitive storage stage for storing a first potential represEntative of the peak level of the input signal and having a selected discharge time constant, a second capacitive storage stage, connected to the first stage, for storing a second potential representative of the peak input signal level, the second stage having a discharge time constant which is large relative to that of the first stage, means for comparing the first potential with a reference potential which is lower than the second potential, and means for reducing the discharge time constant of the second stage in response to decay of the first potential below the reference potential.
 2. A peak detection circuit as claimed in claim 1 wherein the discharge time constant to which the second capacitive storage stage is reduced, when the potential stored by the first stage has decayed below said reference potential, is short relative to the discharge time constant of the first stage.
 3. A peak detection circuit as claimed in claim 2 wherein the means for reducing the discharge time constant of the second capacitive storage stage when the potential stored by the first stage has decayed below said reference potential, includes a transistor which in dependence on the potential stored by the first stage, provides a relatively low impedance discharge path for the second stage.
 4. A peak detection circuit as claimed in claim 2 including a feedback loop for feeding a signal level representative of the potential stored by the second capacitive storage stage to the first capacitive storage stage whereby the charging circuit for the said first stage becomes non-charging when the said signal level representative of the potential stored by the second stage exceeds the input signal level.
 5. A peak detection circuit as claimed in claim 4 including a two-input comparator the said feedback loop and the input for said input signal each being connected to a respective input of the comparator and the comparator being connected to means for controlling the charging current of the first capacitive storage stage such that if the input signal is greater than the signal level on the feedback loop the means for controlling allows charging current to flow whereas if the input signal is lower than the feedback signal the means for controlling cuts off the charging current.
 6. A peak detection circuit as claimed in claim 5 in which the said means for controlling the charging current comprises a transistor switch.
 7. A peak detector circuit as claimed in claim 3 in which the said transistor is controlled by the output of a two input comparator, one input of which is fed with a potential representative of that stored by the first storage stage, and the other input of which is fed with a reference potential.
 8. A peak detection circuit comprising, in combination; a first capacitive storage device; means for providing a fixed impedance discharge path to fixed potential for said first capacitive storage device and having, in combination therewith, a fixed discharge time constant; means for receiving a periodic input signal and for charging said first capacitive storage device in response to and to a peak voltage level related to the peak level of such input signal; a second capacitive storage device; high impedance amplifier means having an input connected to said first capacitive storage device for charging said second capacitive storage device to a voltage level related to said peak voltage level to which said first capacitive storage device is charged; variable impedance means for providing a discharge path to fixed potential for said second capacitive storage device; and means for comparing the instantaneous voltage level on said first capacitive storage device and for controlling said variable impedance means to provide a first discharge time constant for said second capacitive storage device which is long compared to said fixed discharge time constant when the instantaneous voltage level on said first capacitive storage device is above a selected value aNd to provide a second discharge time constant which is short compared to said fixed discharge time constant when said instantaneous voltage level decays below said selected value. 